----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:21:52 04/13/2012 
-- Design Name: 
-- Module Name:    Register_8bit - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Register_8bit is
    Port (  enable,
				reset,
				clk : in  STD_LOGIC;
           reg_in : in  STD_LOGIC_VECTOR (7 downto 0);
           reg_out : out  STD_LOGIC_VECTOR (7 downto 0));
end Register_8bit;

architecture Behavioral of Register_8bit is

begin
	process(clk, reset) begin
		if reset = '1' then 
			reg_out <= "00000000";
		else --clk'event then 
			if enable = '1' then 
				reg_out <= reg_in;
			end if;
		end if;
	end process;

end Behavioral;

